Subject: RE: P1394> Rough SBP-2 & IP1394 core component ROM sizes

From: Nagasaka Fumio <[email-masked]>
Date: Fri, 13 Feb 1998 19:27:28 +0900

I agree with Stephen,
> Also, I don’t believe any of the chip manufacturers support SBP-2 for
both target and initiator.

Do we need to develop a firmware which supports two LINK ICs
one for initiator and one for target? 
I think “yes”. Because typical LINK IC has only one input FIFO in
each chip. And it is very difficult to implement two different software
stack utilizing one i/o channel.
--------------------------------------------
-------------------------------
Fumio Nagasaka
Epson Software Development Laboratory Inc.
Tel +81 268 25 4111,  Fax +81 268 25 4627
E-mail to [email-masked]

		-----Original Message-----
		From:	Stephen Holmstead [SMTP:[email-masked].
com]
		Sent:	Thursday, February 12, 1998 1:30 AM
		To:	'Turner, Randy'; 'Brian Batchelder';
[email-masked]
		Subject:	RE: P1394> Rough SBP-2 & IP1394 core
component ROM sizes

		My experiences in the past is that combining target AND
initiator
		functions into a single device is VERY difficult.  The
complexity of the
		state tables and ambiguities that can arise make it very
difficult.
		Also, I don't believe any of the chip manufacturers
support SBP-2 for
		both target and initiator.  In my opinion, it's NOT just
a matter of
		adding the 15K for the target and 15K for the initiator.
The target and
		initiator have vastly different functions.   Designing a
model that did
		both (well) would be a challenge.  It was problems like
this that fueled
		many of the AEN (asynchronous event notification)
debates.

		Stephen

		> -----Original Message-----
		> From:	Turner, Randy [SMTP:[email-masked]]
		> Sent:	Monday, February 09, 1998 1:03 PM
		> To:	'Brian Batchelder'; [email-masked]
		> Subject:	RE: P1394> Rough SBP-2 & IP1394 core
component ROM sizes
		> 
		> 
		> I am very interested in the combined target/initiator
footprint as
		> well.
		> 
		> Thx
		> 
		> Randy
		> 
		> 
		> 	-----Original Message-----
		> 	From:	Brian Batchelder
[SMTP:[email-masked]]
		> 	Sent:	Monday, February 09, 1998 9:37 AM
		> 	To:	[email-masked]
		> 	Subject:	Re: P1394> Rough SBP-2 & IP1394
core component
		> ROM sizes
		> 
		> 	At 02:04 PM 2/6/98 -0800, Greg Shue wrote:
		> 
		> 	[snip]
		> 
		> 	>I approached them about sharing some rough
estimates of code
		> size
		> 	>for the IP1394 glue, SBP-2 target and
initiator, and 1394 bus
		> 	>manager modules to get a feel for how "heavy"
the protocol
		> 	>implementations really are.  They graciously
shared the flowing
		> 	>estimates with us, and certainly deserve our
thanks.  Since the
		> 	>technology is still being developed, these
implementations are
		> 	>certainly going to be tuned and the numbers
will change a
		> little
		> 	>bit.
		> 	>  Component                Rough ROM size
(KBytes)
		> 	>  ---------
-----------------------
		> 	>  SBP-2 initiator core     15 +/- 5
		> 	>  SBP-2 target core        15 +/- 5  (incl.
Mgmt+Fetch agent,
		> no exec agent)
		> 
		> 	Any idea how big a combined SBP-2
target/initiator would be?
		> 15-30K? ;-)
		> 	[snip]
		> 	Brian
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
		> ‾
		> 	Brian Batchelder      | Hewlett-Packard      |
		> mailto:[email-masked]  
		> 	Connectivity Futurist | 1115 SE 164th Ave.   |
Phone: (360)
		> 212-4107  
		> 	DeskJet Printers      | Vancouver, WA  98684 |
Fax:   (360)
		> 212-4227

---

From: "Michael D. Johas Teener - CTO & CoB, Zayante, Inc" <[email-masked]>
Date: Fri, 13 Feb 1998 09:07:52 -0800

>stack utilizing one i/o channel.

1) All of the Pele-based designs (OpenHCI, among others) do an excellent
job as both initiator and target ... indeed, they can support an almost
unlimited number of simultaneous initiator and target contexts
simultaneously. They are, however, PCI bus master designs ... so unless you
are building a relatively high-end printer, they may not be in your price
range (but check with IC suppliers like Sony, Symbios, and FFM for Pele,
and virtually everyone about OpenHCI).

2) Sony has a fine SBP-2 target part that is also useful for initiator use,
but requires more software and external DMA interaction.

3) The number of input FIFOs is not too important, except as an
optimization, particularly when inbound bus bridging is provided (useful
for CPU-type initiators). The key is to have good receive DMA into the
controller memory.

4) 1394 is quite different from traditional "I/O channels" ... mainly
because it's really a memory bus. If you treat it correctly (as a memory
bus), then it is quite simple to implement multiple stacks using the same
hardware. Indeed, our own proto systems implement as many as 4 protocol
stacks using relatively primative hardware.

===========================================================================
Michael D. Johas Teener, Chief Technical Officer & Chairman of the Board
Zayante, Inc., 269 Mt. Hermon Rd. #111, Scotts Valley, CA 95066-4000, USA
email: [email-masked]    voice: +1-408-461-4901   fax: +1-408-461-1394
======================== http://www.zayante.com ===========================